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GiladA's avatar
GiladA
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Lvds load enable

I design LVDS SERDES IP of 700Mbps Data Rate with external PLL and Serdes factor of 8 on Stratix 10. In the lab i test the design with external loop and encounter a problem with the lsb in the RX (...
Transceiver
  • FvM's avatar
    FvM
    2 years ago

    Hi,
    suggested PLL-parameters are displayed in parameter editor for SERDES IP. Expect -45° (-360/8) load_enable phase shift for 8 bit SERDES.

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,
there's also a phase shift required for load_enable clock.

Question is however, how are you synchronizing LVDS receiver with source?

  • GiladA's avatar
    GiladA
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hi

    the source and receiver are clock freq synchronize, so i use DPA block to synchronize.

    what is the phase shift required for load_enable?

    is it correct to define low freq (87.5MHz in my case) and duty cycle of 12.5?

    Thanks Gilad

    • FvM's avatar
      FvM
      Icon for Super Contributor rankSuper Contributor
      2 years ago

      Hi,
      suggested PLL-parameters are displayed in parameter editor for SERDES IP. Expect -45° (-360/8) load_enable phase shift for 8 bit SERDES.