GiladA
New Contributor
2 years agoLvds load enable
I design LVDS SERDES IP of 700Mbps Data Rate with external PLL and Serdes factor of 8 on Stratix 10.
In the lab i test the design with external loop and encounter a problem with the lsb in the RX (in the simulation it all works well).
I suspect to have a problem with the load_enable configuration in the pll.
I configure LVDS Fast clock as 700 MHz and load_enable as 87.5 MHz with duty cycle of 12.5 in order to create enable every 8 fast clock cycle.
Is it the correct way to create load_enable or there are other alternative ?
Thanks Gilad
In the lab i test the design with external loop and encounter a problem with the lsb in the RX (in the simulation it all works well).
I suspect to have a problem with the load_enable configuration in the pll.
I configure LVDS Fast clock as 700 MHz and load_enable as 87.5 MHz with duty cycle of 12.5 in order to create enable every 8 fast clock cycle.
Is it the correct way to create load_enable or there are other alternative ?
Thanks Gilad
Hi,
suggested PLL-parameters are displayed in parameter editor for SERDES IP. Expect -45° (-360/8) load_enable phase shift for 8 bit SERDES.