If TimeQuest is analyzing the paths as register-to-register (clocked) paths, then you must be feeding the input to the combinatorial logic from registers and capturing the result in registers.
To tell TimeQuest that the input registers will not be updated for several clocks, allowing the output to become valid, you must assign a multi-cycle constraint. For example, if you constrain just the clock (a single clock cycle for register-to-register paths) and the path fails by 2.1 clock periods, then placing a 3 clock cycle multi-cycle contraint will tell TimeQuest that this particular register-to-register path is allowed 3 times the clock period to settle. Its then up to your control logic to ensure that the inputs are held valid, and the output registers enabled 3 clocks later.
Look for multi-cycle contraints in the TimeQuest documents and in Rysc's TimeQuest guide on the AlteraWiki.
Cheers,
Dave