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Why do you need such a huge divider?
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I'm implementing a precision time protocol PTP slave.
For this I have to make a real time clock with adjustable speed.
To realize this i increas the real time clock with a timestep at each clock cycle.
Furthermore i measure elapsed time intervals at the PTP Master and the PTP slave.
If the slave and master intervals are not equal i have to adjust the timestep.
Such interval consist of 80 bit nanoseconds and 16 bit subnanoseconds (nanoseconds*2^16) = 96 bit.
To adjust the timestep i want to calculate how many clock cycles of the slave created the current error beetween slave and master
and with this the offset which have to add to the old timestep to correct this error.
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Do you need a pipelined design? Can you suffer some wait cycles? You could do a bit by bit difference method if you have some spare clock cycles. See the Advanced Synthesis Cookbook for an example (
http://www.altera.com/literature/manual/cookbook.zip)
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I need no pipelined design.
I can wait some cycles but this will rise the overall error.
I will have a look in the Cookbook.
Honored Contributor
