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Altera_Forum
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7 years ago

LPM Counter Output Resetting To Wrong Value

Hello, I am using the lpm_counter Megafunction and I am observing incorrect behavior at the counter Q output on 20% of the FPGA design builds. In all the builds that fail, the counter outp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

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Hi kaz,

The sclr is truly a synchronous clear. That signal is already registered with same clock that is used for the lpm counter clock input.

Thanks!

John

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In that case I assume your observation is wrong as counters are last to be buggy. Try signaltap.

Or try infer a counter away from lpm and lower level tools.