Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

LPM Counter Output Resetting To Wrong Value

Hello, I am using the lpm_counter Megafunction and I am observing incorrect behavior at the counter Q output on 20% of the FPGA design builds. In all the builds that fail, the counter outp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Hi kaz,

The sclr is truly a synchronous clear. That signal is already registered with same clock that is used for the lpm counter clock input.

Thanks!

John