Low latency phy IP receiver CDR clock loss lock！

Hello ！I want to implementate a transceiver on de5-net board!Now there are some problems,in my projects debuging.

my instant of low latency phy is configured as: standard datapath, duplex mode,6000Mbps data rate, and the refclk is 150MHz,pll is ATX PLL, fpga-to-pcs width is 40.

when i reset the phy ip,the tx_ready is pull high,but rx_ready never asserts,and the pll_locked just stay high for a clock period.My signaltap clock is rx_clkout of low latency phy ip.