Low Latency PHY IP Core Transmitter

Question

Hello everyone,

For the project I am working with, I need to use my stratix V GT transceiver SI board as a transmitter . I dont need to use the PRBS generator, the data i will send i already created. So basically what i need is by using the low latency PHY IP-Core transmit the data ( defined in an array ) from SMA ports. I wrote a VHDL code for this but I cannot simulate it . it gives an error when the nativelink program is starting. I have added the error log . Can someone please help me with this?

Also, is there an example code for this purpose ( i thought there might be something due to it is really basic).

Thank you in advance.

Info: Start Nativelink Simulation process

executing command line: ip-make-simscript --nativelink-mode --output-directory=Tx1_iputf_input --spd=Z:/Chalmers/1-1/Project/FPGA/Projects/Learning and Trials/Transmitter 1/tx_core.spd

Internal error: Failed to run ip-make-simscript: 2016.10.19.10:35:53 Error: Unrecognized switch 1

2016.10.19.10:35:53 Error: Unrecognized switch 2

2016.10.19.10:35:53 Error: Unrecognized switch 3

Internal error: Failed to run ip-make-simscript: 2016.10.19.10:35:53 Error: Unrecognized switch 1

2016.10.19.10:35:53 Error: Unrecognized switch 2

2016.10.19.10:35:53 Error: Unrecognized switch 3

Error: NativeLink simulation flow was NOT successful

================The following additional information is provided to help identify the cause of error while running nativelink scripts=================

Nativelink TCL script failed with errorCode: 1

Nativelink TCL script failed with errorInfo: 1

(procedure "iputf_call_script_gen" line 25)

invoked from within

"iputf_call_script_gen $spd_file_list"

(procedure "iputf_setup_info" line 45)

invoked from within

"iputf_setup_info"

(procedure "run_eda_simulation_tool" line 178)

invoked from within

"run_eda_simulation_tool eda_opts_hash"

aajit2 · Answer

Hi I also ran into a similar problem when trying to simulate my code using ModelSim, have you managed to solve it yet?

bitwise · Answer

You need to configure two areas in QuartusII for the Modelsim native link to work then recompile your project:

STEP 1

In QuartusII select "Tools / Options / EDA Tool Options" then fill in the Modelsim (which means the version you purchase from Mentor) or Modelsim-Altera (the version from Intel) box with the path to the binaries for Modelsim. For example, if you have the Modelsim-Altera installed along with QuartusII version 17.0 then your path would be something like c:\Altera\17.0\modelsim_ae\win32aloem.

STEP 2

With your project open in QuartusII, select "Assignments / Settings / EDA Tool Settings / Simulation" and use the pull-down to select your simulation tools which was configured in step 1 (Modelsim or Modelsim-Altera). Set your HDL choice next to indicate which language you wish to simulate. There are additional settings which you can tweak later, but for now leave those in their default states.

STEP 3

Compile your project. You should see references to the EDA netlist writer during compilation; that is the module that writes your project's simulation scripts. After compilation completes you should be able to launch Modelsim from QuartusII by selecting "Tools / Run Simulation Tool / RTL Simulation".

harikrishnan · Answer

Hi ,I followed these 3 steps and I still face this issue while compiling with a PLL ip.

chami · Answer

I am facing the same issues, and the suggested steps will not resolve the problem. It seems to be specific to the project with a hard IP, as I can simulate other projects without any issues.

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Low Latency PHY IP Core Transmitter

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