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PVanL's avatar
PVanL
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Low latency Ethernet 10R Reference Design. How to modify the behaviour of the testbench?

I understand the "avalon_if_param_pkg" is used to configure the behaviour of the Avalon Interfaces. Eth_register_map_params_pkg to configure the inside of the packet. I want to change the gaps betwee...
PVanL's avatar
PVanL
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hi Deshil,

Sorry for not answering earlier. I solved now all my hardware issues with my version of PHY connected to the INTEL MAC. Thanks for that.

I found several UG's and AN documents describing the PCIexpress IP and Examples. At a certain moment in time, i managed to generate a .par file, from which QUARTUS lite 18.0 generated PCIE- IP. However, i cannot find a way to generate the <pcie_a10_hip_0_example_design> as described in ux-dex-a10-pcie-avst.pdf, found at https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-a10-pcie-avst.pdf.

Can your PCI Express collegue support me in generating this design example. Second question to him: there is a choice between the avalon-st protocol implementation, and a avalon-mm implementation. As the Low Latency MAC interfaces with an Avalon-ST interface, I thought this would be the more easy choice. Is that right, or are there reasons to use the mm version? Regards, Pieter