Low latency Ethernet 10R Reference Design. How to modify the behaviour of the testbench?

Hi Pieter,

Sorry for getting back late to you.

It seems like you are experimenting with different design logic to interact with 10G MAC and you also build your own Ethernet traffic generator/checker ? and you are seeing weird behaviour on your own Ethernet traffic generator/checker or are you trying to feedback there is some issue in Ethernet example design ?

• Did you enable ECC option in 10G MAC so that you can check for potential error bit with ECC error correction signal ?
• There are some timing diagram on both Avalon ST Tx and Rx interface data transfer that you can cross check as expected reference vs your design data transfer
• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_32b_10g_ethernet_mac.pdf

Thanks for the detail explanation but sorry, I don't think I understand and following your issue here.

• We don't restrict how customer build their user logic to interact with MAC.
• If adding extra buffer/FIFO helps to smooth out the data traffic transfer pipeline then it's not a bad choice either.
• Also always ensure design is able to meet timing closure in Quartus Time Quest Analysis. Sometime weird result behaviour is due to data transfer failure caused by design timing issue.

Thanks.

Regards,

dlim