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PVanL's avatar
PVanL
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Low latency Ethernet 10R Reference Design. How to modify the behaviour of the testbench?

I understand the "avalon_if_param_pkg" is used to configure the behaviour of the Avalon Interfaces. Eth_register_map_params_pkg to configure the inside of the packet. I want to change the gaps betwee...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Pieter,

I looked at the LL 10G example design and I can see that the Ethernet traffic generator is controlled by a BFM (avalon_driver.sv) which is then further controlled by Altera Avalon BFM (csr, st Tx and st Rx)

  • alt_em10g32_0_EXAMPLE_DESIGN\LL10G_10GBASER\simulation\ed_sim\models\avalon_driver.sv
  • /ip/altera/sopc_builder_ip/verification/altera_avalon_mm_master_bfm/altera_avalon_mm_master_bfm.sv
  • /ip/altera/sopc_builder_ip/verification/altera_avalon_st_sink_bfm/altera_avalon_st_sink_bfm.sv
  • /ip/altera/sopc_builder_ip/verification/altera_avalon_st_source_bfm/altera_avalon_st_source_bfm.sv

To be honest, it's complicated and not easy to decode these BFM. I am sorry. I can point you some direction but I won't be able to do much help for you.

  • Perhaps you can also consider to re-write your own test bench as well

Else If you look at the testbench top level file again (tb_top.v), look like from line 640 onwards in function (if (id == 0),

  • Looks like user is able to tune some setting provided you spend time to understand the BFM address mapping.
  • Feel free to explore it

Thanks.

Regards,

dlim

  • PVanL's avatar
    PVanL
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago
    Hi Deshil, Thanks for looking at this, it is indeed not easy, I am afraid I have to study Verilog manuals, some parts of the code are hard to read (in the US you probably feel the same about vhdl). There are four workarounds: 1/ study the BFM models as you suggested, 2/ rewrite the testbench (that is a hard one, as the compare function is essential that I do not yet fully understand), 3/ use the atlanta protocol, (used in Avalon driver, with the start/end of packet indicator, I assume I can raise the ‘ready’ indicator to ‘0’ to create an artificial idle period), and 4/ finish the fifo in which I create also idles. I am almost done with 4/, but 3/ seems the more simple approach that I though of halfway building nbr 4/. Regards, Pieter