Low latency Ethernet 10R Reference Design. How to modify the behaviour of the testbench?

Hi Dlim,

Thanks for responding to my question.

The example is "Scalable Low Latency Ethernet 10G MAC Intel FPGAIP",

see https://fpgacloud.intel.com/devstore/platform/14.0.0/Standard/scalable-ll-ethernet-10g-mac-with-10g-baser-phy-design-example/?wapkw=LL%20Ethernet%2010G%20MAC,

and see amongst others "ug-20162_LL_MAC_cyclone10GX" manual.

Or the UG-01144, see https://www.intel.com/content/www/us/en/programmable/documentation/bhc1395127830032.html

I am not sure if i changed any settings, a least not intentionally, except for some (irrelevant) timing in the testbench (to make it faster), What i am sure about is that i replaced the INTEL PHY with my own PHY, with some specific features. I got that working.

The configuration I use is 10 Gbps, 1 channel, xgmii 64 + 8 bit.

Now i want to change the testbench (tb_top.sv in the example), such that that there are not exclusively packets of 75 bytes (including preamble, CRC, closing byte "FD")

The packets always end with last2 valid bytes (when the packet starts in hte second half of the 64 bit dataword, or with last6 valid bytes (when the packet starts on the first half of the 64 bit dataword.

I also want to check my PHY on last1, last2...last8 valid byte at the end of packet.

The packets are very tight to each other: 8 byte or 12 idle byte, see examples below (where "07" is an indication of "idle")

time(nsec) data                               cntr
3789 istin A3208DD2E6FB626E 00000000 
3796 istin 0707070707FD2B8F 11111100 
3802 istin 555555FB07070707 00011111 
3809 istin 00000000D5555555 00000000 
3815 istin EEAACC88CCEE0000 00000000

(example 8 byte from MAC), or

3853 istin CCBCF5E2A39F4168
3860 istin 07FD2B8FA320C1C1
3866 istin 0707070707070707
3873 istin 555555FB07070707
3879 istin 00000000D5555555
3885 istin EEAACC88CCEE0000

(example 12 byte from MAC)

I want to be able to change this gap of 8 or 12 byte to any multiple of N * 4 bytes. (exclusive of the 0, 1, 2, 3 last idle byte at the end of a packet)

Now i am building a fifo between eth_generator and the MAC to create those gaps, but that is not a very elegant way ).

I believe the clue is somewhere in:

*  "avalon_if_parameter_pkg.sv"  : for packet length
* "default_test_params_pkg.sv" : i thought for a moment change "INSERT PAD" from 1 to 5, but this does not result in a visible change anywhere
* "eth_mac_frame"  : there is a function "virtual function void insert_payload(ref bit [7:0] frame_data[], input bit [7:0] payload[])" (i am more VHDL then Verilog, what functionality is this virtual void?)
* "eth_register_map_params_pkg.sv" seems to be address map

I attached a part of the transcript, from vlog command onwards.

line 3 - 100 : compiling

line 101 - 314 : elaboration

line 315 - 369 : warnings

line 377 - 443 : starting of testbench

line 446 - 626 : warnings during runtime (not so relevant, those appear in my PHY, not in INTEL's), mainly searching for blocklock and the processing of 'x' s

line 626 -677 : receipt of packets

line 678 - 683 : processing compare

line 688 - 756 : reporting compare.

Looking forward to your advice.

Regards, Pieter