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SKinz's avatar
SKinz
Icon for New Contributor rankNew Contributor
6 years ago

Low latency 100GE core with CAUI-4 sends bit errors at regular intervals to switch

We've implement the low latency 100GE core with CAUI-4 in an Arria10 GT. About every 30 minutes the 100GE switch reports a burst of errors and takes the interface down. We suspect that there is an is...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago
Hi Skip, when the interface is down, does reset of the 100G IP can bring the link up again, or it can recover without reset ? Does the same problem occur if you perform an external loopback test (FPGA TX -> Cable -> FPGA RX)? Any frame error (from statistic counter) observed before the link down? Is the refclk located at the same side with the transceiver bank? Regards -SK Lim