Legacy DDR compilation error

Hi,

I just found the error:

The requirements for when to use external resynch clock must have changed from ver 8.0 to 8.1. So the ddr compiler automatically adds a resynch clock when you recompile the core. (In my case)

The BIG PROBLEM is that quartus does not flag the fact that the resynch clock is unconnected, it just compiles the project.

The next issue is the fact that the scripts that the timing analyzer sets up cannot figure out that the resynch clock from the pll is delayed properly (303 deg). So it flags an timing error.

I have to add that I have checked the reports in the fitter section, and the delay is properly reported, so I am not sure what do to at this point.

Solution? Stick to version 8.0 of the legacy ddr core.

I have not reported this issue to altera.

apus