Legacy Controller

1. can we generate programming file by replacing control logic in legacy controller by our control logic?

2. can we do the post pnr netlist simulation for the same(our control logic + legacy phy)?

3. which mode does the legacy controller support - tethered or untethered? if untetherd, then what s the life of this megafunction?

there is a constraint editor page on megawizard. i am not editing it. i just left all the fields blank, because i did not understand what it is meant for? i edited the pins under assignment tab and then did the compilation. the target device is stratixiigx 1152. please find below the post summary timing report:

note: found a clock output pin: clk_to_sdram[0]

note: found a clock output pin: clk_to_sdram_n[0]

running ddr system timing analysis equations.. pwd:/ipprojects/gmc/harshbandil/legacy_phy

note: speed grade c3 used for analysis

critwarning: board timings: you have selected one or more default board trace delays. please modify 'fpga clock output..' and 'memory dq/dqs..' fields to reflect requirements for your specific system so that the correct timing set-up and analysis can be performed.

note: for a 'custom' memory device, please ensure that your chosen cl is compatible with your clock speed selection

ddr read data capture: ddr data to dqs strobe edges at capture registers.

setup slack is 318 ps associated with pin 'ddr2_dq[6]' ( variation port 'dq(6)', 'dq_captured_falling')

hold slack is 782 ps associated with pin 'ddr2_dq[0]' ( variation port 'dq(0)', 'dq_captured_rising')

read data resynchronisation: captured data to resync clock at resync registers ('resynched_data').

warning: setup slack is -3620 ps associated with pin 'ddr2_dq[4]' ( variation port 'dq(4)', 'dq_captured_rising') ( total of 16 paths with negative slack)

hold slack is 3385 ps associated with pin 'ddr2_dq[1]' ( variation port 'dq(1)', 'dq_captured_falling')

read postamble enable: enable-release to dqs strobe postamble period at negative-edge capture registers.

setup slack is 1187 ps associated with pin 'ddr2_dq[0]' ( variation port 'dq(0)', 'dq_captured_rising')

hold slack is guaranteed by design to always be positive for stratix ii

read postamble control: preset-release ('dq_enable_reset') to dqs strobe negative edges at postamble register ('dq_enable').

setup slack is 5407 ps associated with pin 'ddr2_dq[0]' ( variation port 'dq(0)', 'dq_captured_rising')

warning: hold slack is -1781 ps associated with pin 'ddr2_dq[0]' ( variation port 'dq(0)', 'dq_captured_rising') ( total of 16 paths with negative slack).

how can we suppress these errors????

regards,

harsh bandil