Honored Contributor
Honored ContributorAh, you're correct about ready latency of zero - I'm just so accustomed to ready latency of one since that's what's employed with the video "profile" atop Avalon-ST. The reason for that is just for sake of pipelining, it gets difficult when you have a long pipe that has to stop *on a dime* as soon as ready deasserts from your sink. Latency of one allows you to have a little bit of inertia, and in video designs we're often pushing the limits of devices' clock rates, even if that's just doing wimpy old 1080p on a Cyclone-class device :)
Sadly though the same calculus has to apply in my case - no sooner than I have standard-def video happily bridging across a 1G network, I'm immediately off to hot-rodding everything to run 3G-SDI across 10G Ethernet and all the clock rates go up for both the video and network clock domains. So I'm reluctant to predicate everything on being able to stretch across parts of the chip and still meet timing with the ability to throttle the pipeline with zero cycles of "notice" from the sinks. I'll stick with my workaround for now and see if I can get anyone to pay attention to me. For what it's worth, I can do *exactly* what I want to do with X**inx Platform Studio, have been for several years... ...maybe that will do it :D
