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per the Avalon-ST spec, data symbols are always transferred on every cycle in which valid is asserted, it's merely up to the Source to deassert valid within the appropriate ready latency
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In my experience, with '0 ready latency' the data
only gets transferred when both 'ready' and 'valid' are asserted. I have never used anything else than 0 ready latency, though. I don't see the use (in what I design) as well.
To my idea you could achieve what you want (to some extent) using the two ST-signals at hand: the source valid goes high to signal the request, the arbiter keeps ready de-asserted until ready to accept and then asserts ready for one cycle only, the source in turn de-asserts it's valid and then waits for the ready to be re-asserted again by the arbiter to start the rest of the stream. Again assuming 0 ready latency.
valid 000011111000000111111111111
ready 000000001000001111111111111
But you are quite right: Qsys is a bit of a straitjacket and it certainly would be an enhancement if we could add the kind of signalling you propose, as well as other out_of_band signals. I personally had a hard time with the enforced Data Width / Symbol Width between sinks and sources. E.g. an ST-splitter is used to divide a data stream into two processing chains, each operating on part of the data, Qsys doesn't allow this. So I had to write my own 'adapter' for this. I can't deny it was fun and I learned a bit of Tcl.
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