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Altera_Forum's avatar
Altera_Forum
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12 years ago

LAB Optimization

Hi,

I've developed an IP Core, were there's a lot of logic operations (xor). All of them are done in a single clock cycle. My IP uses 35.000 LUTs out of 55.000 availalbe in my ARRIA II GX device. Compilation goes ok, but fitter says that he needs 2900LABs (2500 available). I've tried all the area optimizations available in the Resource Advisor. What can i do to make this code fit my device? It fits when i disconnect my IP Core from Onchip Ram Memory which is my interface to connect with external microprocessor (through PCIExpress). Why is this connection so large? I have 2 memories 128 bits wide, and 1 mem 256 bit wide. All of them are dual port altsyncrams, with 32 bit itf from PCIExpress.

Thank You.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    LUTs are not a good metric. A 6-input LUT uses the whole ALM, while a 4-input LUT uses half of it, i.e. you can get twice as many 4LUTs, 3LUTs, 2LUTs as 6LUTs. (5LUTs can usually be packed with 3LUTs, or share an input. I believe the handbook shows all the combinations). The Logic Utilization is the number you should be looking at to determine how full it is. In 12.1 the numbers were redone to use ALMs instead of LUTs, and is much easier to understand. The Logic Utilization is the same in 12.1, just the breakdown is done differently. (Before 12.1 it reported LUTs as a number that might be too low, but later on accounted for "Unpairable LUTs" because of 6,7 input LUTs, etc. If you ignore the Logic Utilization and just looked at LUTs without looking at the rest, you were not getting the full story...)

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I have quartus 12.1sp1. This is my Resource Usage Report:

    ALUTs Used 36,124 / 50,600 ( 71 % )

    -- Combinational ALUTs 36,124 / 50,600 ( 71 % )

    -- Memory ALUTs 0 / 25,300 ( 0 % )

    -- LUT_REGs 0 / 50,600 ( 0 % )

    Dedicated logic registers 5,962 / 50,600 ( 12 % )

    Combinational ALUT usage by number of inputs

    -- 7 input functions 347

    -- 6 input functions 21009

    -- 5 input functions 4256

    -- 4 input functions 4482

    -- <=3 input functions 6030

    Combinational ALUTs by mode

    -- normal mode 34318

    -- extended LUT mode 347

    -- arithmetic mode 1249

    -- shared arithmetic mode 210

    Logic utilization 58,120 / 50,600 ( 115 % )

    -- Difficulty Clustering Design No-Fit

    -- Combinational ALUT/register pairs used in final Placement 37044

    -- Combinational with no register 31082

    -- Register only 920

    -- Combinational with a register 5042

    -- Estimated pairs recoverable by pairing ALUTs and registers as design grows 0

    -- Estimated Combinational ALUT/register pairs unavailable 21076

    -- Unavailable due to Memory LAB use 0

    -- Unavailable due to unpartnered 7 LUTs 347

    -- Unavailable due to unpartnered 6 LUTs 20553

    -- Unavailable due to unpartnered 5 LUTs 34

    -- Unavailable due to LAB-wide signal conflicts 20

    -- Unavailable due to LAB input limits 65

    -- Unavailable due to location constrained logic 1

    Total registers* 5962

    -- Dedicated logic registers 5,962 / 51,336 ( 12 % )

    -- I/O registers 0 / 2,232 ( 0 % )

    -- LUT_REGs 0

    ALMs: partially or completely used 29,001 / 25,300 ( 115 % )

    Total LABs: partially or completely used 2,906 / 2,530 ( 115 % )

    -- Logic LABs 2,906 / 2,906 ( 100 % )

    -- Memory LABs 0 / 2,906 ( 0 % )

    Virtual pins 0

    I/O pins 82 / 404 ( 20 % )

    -- Clock pins 0 / 10 ( 0 % )

    -- Dedicated input pins 0 / 28 ( 0 % )

    Global signals 17

    M9K blocks 64 / 495 ( 13 % )

    Total MLAB memory bits 0

    Total block memory bits 125,984 / 4,561,920 ( 3 % )

    Total block memory implementation bits 589,824 / 4,561,920 ( 13 % )

    DSP block 18-bit elements 0 / 312 ( 0 % )

    PLLs 1 / 4 ( 25 % )

    Global clocks 16 / 16 ( 100 % )

    Quadrant clocks 0 / 48 ( 0 % )

    Periphery clocks 0 / 50 ( 0 % )

    SERDES receivers 0 / 28 ( 0 % )

    JTAGs 0 / 1 ( 0 % )

    ASMI blocks 0 / 1 ( 0 % )

    CRC blocks 0 / 1 ( 0 % )

    Remote update blocks 0 / 1 ( 0 % )

    GXB Receiver channel PCSs 1 / 8 ( 13 % )

    GXB Receiver channel PMAs 1 / 8 ( 13 % )

    GXB Transmitter channel PCSs 1 / 8 ( 13 % )

    GXB Transmitter channel PMAs 1 / 8 ( 13 % )

    HSSI CMU PLLs 1 / 4 ( 25 % )

    Impedance control blocks 0 / 3 ( 0 % )

    Maximum fan-out 3662

    Highest non-global fan-out 1696

    Total fan-out 221200

    Average fan-out 5.12
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Are you sure this is 12.1sp1? It looks like a report from before 12.1. Regardless, the Logic Utilization is at 115%, so it won't fit. If you look at the breakdown, the big killer is 6-LUTs, as your design has 20K and therefore the whole ALM is lost:

    -- Unavailable due to unpartnered 6 LUTs 20553

    It's basically like adding 20K to your ALUT count.