JESD204B Multi-Link Implementation with AD9695 ADCs Having Different Lane Counts (L=4 and L=2)

Hi,

My understanding is that you are using the JESD204B RX IP to interface with three ADCs, with link configurations of L=4, L=4, and L=2.

Since there are 3 ADCs, the most robust implementation would be to instantiate three separate single-link JESD204B RX IP cores.

For proper Subclass 1 synchronization and reliable operation across the three links, please consider the following:

1. Maintain a common SYSREF and device-clock scheme across the FPGA and all ADCs, with careful trace matching and minimal SYSREF phase offset. 
2. Keep SYNC~ handling aligned across all three links. In multi-link synchronization schemes, the DEV_SYNC_N signals from the IP cores can be combined as described in the JESD204B guidance. 
3. Ensure the link clock and frame clock remain synchronous through the selected transceiver PLL and clocking architecture.

Overall, using separate IP instances is the safest and most straightforward approach for this configuration.

Thank you.