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VBalamurugan29's avatar
VBalamurugan29
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2 months ago

JESD204B Multi-Link Implementation with AD9695 ADCs Having Different Lane Counts (L=4 and L=2)

Hello Intel Community, I am currently working on a multi-chip ADC design using the AD9695 with the JESD204B interface on an Intel Stratix 10 FPGA. I am using the JESD204B Intel FPGA IP core and have...
Jesd
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VBalamurugan29's avatar
VBalamurugan29
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2 months ago

Hi all,
can anyone  here to give solution for this thread ?

  • CheepinC_altera's avatar
    CheepinC_altera
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    2 months ago

    Hi,

     

    Thank you for filing this case and sharing the details. Sorry as I might have overlooked this. Please allow me some time to look into your queries and get back to you. Thank you.

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    2 months ago

    Hi,

     

    Just to follow up if there is any inquiry. Thank you.