Honored Contributor
Honored ContributorI have a similar issue with the Stratix V dev-kit in which I want to connect 12 JESD lines and there are only 12 XCVRs available and none of the dedicated reference clocks are routed out to HSMC connectors. I spent a while looking over the documentation and found that it is actually possible to use standard clock inputs for the high speed transceivers. So far I have only test compiled my design and it fits successfully - still waiting on PCBs before I can actually test it. With that I mind I thought I would selfishly help you in the hope you can test it out and let me know if the following works for you.
The XCVRs have three possible clock sources. In order of preference, they are: (1) dedicated XCVR refclk inputs (non broken out). (2) spare XCVR RX channels (doesn't help either of us). (3) the output of an FPLL. Option (3) may be the saviour in both our designs. It is possible to use the output of a fractional PLL in the PLL Strip to clock the transceivers. The FPLL can in turn use a standard clock input as its reference clock. This is a bit of an obscure way to do it, but should work. Looking at the CV datasheet, for your device it appears there is indeed a PLL strip which will help. Specifically FRACTIONALPLL_X0_Y64 and FRACTIONALPLL_X0_Y81 can both be clocked from the dedicated reference clock inputs on HSMC_A_CLK_IN_1, HSMC_A_CLK_IN_2, and HSMC_B_CLK_IN_2. This is good because it means there is a way to get the spare clocks into the FPLLs and hence into the XCVRs. My suggestion looking at the CV dev kit is for you to use the HSMC *B* connector. The reason for this is it means all of the XCVRs are grouped together which will make life easier (both in terms of timing, and fitting). If you connect to HSMC B, and then use the spare device clock, I believe pins J20 and K19. This will bring in your device clock. Next, instantiate a fractional PLL which uses this clock as the input, and then produces 3 output clocks, the two you need anyway for the JESD core (frame clock and link clock), and a third which is the same frequency as the input clock which you will feed as the device clock to the JESD core. With these connections the fitter should be able to map the design into either of the two FPLL locations I mentioned above. --- As I say, if you can try this out and let me know if it works, that would be great.
