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CHebl's avatar
CHebl
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6 years ago

JESD204 IP-Core occasionally receives wrong data in internal loopback mode

I'm currently trying to implement the JESD204-IP Core to receive data from an ADC on an Arria 10 using Quartus Prime v18.1. To test the receiver I implemented both channels (TX and RX) of the Transce...
CHebl's avatar
CHebl
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6 years ago

Hi Nathan,

sorry for coming back to you this late.

I configured the PLL, that's generating the link clock (I switched the RX Link Clock from CDR to PLL clock), to produce another clock at twice the frequency and used it to sample the data with a pipelining factor of 1.

Another point I noticed is, that all the wrong received words have in common, that the byte patterns are repeated eg. 0x5959, 0x0202, 0x0303 etc.

Furthermore its the most significant 8 bit, that are being duplicated to the least significant 8 bit (N=16). This is something I observe on the interface between my datapath and the IP-Core, so it isn't due to data reordering on my part (imo).

This problem also occurs when using an external ADC from Analog Devices, so i believe the problem to be in the recieve path.

Regards,

Chris