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CHebl's avatar
CHebl
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6 years ago

JESD204 IP-Core occasionally receives wrong data in internal loopback mode

I'm currently trying to implement the JESD204-IP Core to receive data from an ADC on an Arria 10 using Quartus Prime v18.1. To test the receiver I implemented both channels (TX and RX) of the Transce...
CHebl's avatar
CHebl
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6 years ago

Hi Nathan,

many thanks for your answer.

I've tried oversampling the output data, but the wrong received words are stable. I've also been using the CDR clock for sampling the data and wouldn't expect timing issues there, but the result was the same.

I've also checked the code_err signals in the RX 8b10b block and those aren't being asserted either.

I'm a little bit at a loss here.

Best regards,

Chris