JESD IP core: Same link clock shared between all transciever lanes

--- Quote Start ---

Hi Gowtham,

Given that the ADCs are synchronous, then yes, a single reference clock at the FPGA should be sufficient. However, you should synthesize an example design to make sure that the FPGA clock pin you select is acceptable. For example, I have run tests where REFCLK inputs on the left-side of a device are not acceptable to transceiver blocks on the right-side of the device, so in that case, I have explicitly designed the boards with external clock fanout ICs and made the FPGA REFCLK inputs programmable via those external devices (SiLabs and TI have parts that are specified for 10Gbps performance).

So, the only answer you should accept in this regard is the answer provided by Quartus :)

Which Arria V GZ board are you using? TI have an FMC development kit

http://www.ti.com/tool/tsw14j56evm

That I am using now. I can give you a basic top-level example design that includes the DDR interface. I'm just starting to work with the transceiver IP now. Once I have that working, I'll look at the JESD204B IP cores. I will then test the ADS42JB69EVM.

Cheers,

Dave

--- Quote End ---

Hi Dave,

Thanks for the info. I am doing a study about Arria V GZ transceivers and JESD IP core in the same tsw14j56evm.

Thanks,

Gowtham