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Did you look at the JESD204B standard?
http://www.jedec.org/sites/default/files/docs/jesd204b.pdf (You have to register, but the standard is free)
The links are encoded, so in general you could create a system with reference oscillators, and allow the clock-and-data recovery unit to track any phase/frequency-shifts between those oscillators, just as you would in a network setup. However, if you are using multiple ADCs, and those ADCs are synchronous, then its just as easy to use a common reference clock for all the ADCs and FPGAs.
Analog Devices has an article on JESD204B
http://www.analog.com/static/imported-files/tech_articles/jesd204b-survival-guide.pdf What are you trying to do?
Cheers,
Dave
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Hi Dave,
Thanks for the info I am actually interfacing multiple synchronous ADCs through JESD with Arria V GZ and would like to know if one common reference clock pin is enough in the FPGA side for the all the Lanes. We know that for L transceiver channels in the FPGA side we have L/3 exteranl reference clock pins dedicated. Hence I would like to know if we could only one of the external reference clock pin can be used for all the channel PLLs(transceivers).
Thanks in advance,
Gowtham
Honored Contributor
