JESD data rate Qsys / Link Clock

Hi!

I faced the similar problem)

1. If we consider Altera IP Core the data rate is supposed to be the data rate per EACH lane (NOT total data rate per all link lanes).

2. Link clock == Data rate (per each lane)/40

User Guide, p 4-19

"The timing reference for the JESD204B IP core.The

link clock runs at data rate/40 because the IP core is

operating in a 32-bit data bus architecture after 8B/

10B encoding."

As far as I understood link clock == 125MHz, frame clock == 250MHz

Best regards!