Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Issues with Arria10 Transceiver during Simulations

I have run into an issue while simulating an Arria10 Transceiver configured for Rx using DeSerialize X2 option. It is configured for 6Gbit operation and the FPGA interface is 40-bit. The problem is...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I've tried a few different reference clock frequencies for both the ATX pll and the for CDR reference clock. What I have found is that 100MHz and 125Mhz do not work, but if I use 150Mhz the problem goes away. Are there simulation constraints that I'm not aware of?

Matt