Issues using ST-Avalon root port on Stratix 10 MX development Kit

Hello @NathanR_Intel​ ,

Thank you very much, it works!

I don't understand one thing with these pins. I already developed PCIe interface with intel FPGA Stratix 5, Arria 10 and endpoint with Stratix 10 and I hade only to declare positive pins of PCIe and everything work.

Now if I use your solution I declare the 8 pins pcie_rx_rc[0] to pcie_rx_rc[7] by negative pins and the others by the positive ones.

I think there is maybe a mistake in the schematic for the root port.

Best regards,

Amine