Forum Discussion
New ContributorIssue with Simulation Stalling in Intel P-Tile Streaming PCIe Gen4 x8 Example Design
Hi,
I am Wincent, Application Engineer from Altera.
We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries.
Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended.
May I know which Questasim version that you are using?
There is an known issue we try to fix for the P-tile simulation tools.
To work around this problem, use Siemens* Questa Sim-64 2022.2. Starting in the Intel® Quartus® Prime Software version 23.3, solve this issue by adding this command " set USER_DEFINED_ELAB_OPTIONS "-voptargs=\"-noprotectopt\" before running simulation in the Siemens* Questa Sim.
Detail you may refer to https://www.intel.com/content/www/us/en/support/programmable/articles/000092901.html
Hope that is able to help you to move forward,
Regards,
Wincent_Intel
Regular ContributorHi Thana,
Sorry for late, I was occupied with some other important agenda.
I am able to run and capture the signal via Questa Sim 2023.4 version based on your device#
I forget to record the time while leaving it run overtime, it shall be less than 6-8 hours
Regards,
Wincent
New ContributorHi Winicent,
After configuring the P-Tile as a Native Endpoint IP and providing all the necessary settings in the GUI, if we program it onto the Stratix 10 board, will the enumeration take place? How can we verify if the enumeration was successful? We are using a Stratix 10 board with Quartus version 20.3. Which signals, such as ninit_done, ref_clk[1:0], and reset, need to be connected for the P-Tile IP? Is there a user guide that explicitly outlines these requirements?
Regards
Thanavignesh
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