Forum Discussion
New ContributorIssue with Simulation Stalling in Intel P-Tile Streaming PCIe Gen4 x8 Example Design
Hi,
I am Wincent, Application Engineer from Altera.
We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries.
Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended.
May I know which Questasim version that you are using?
There is an known issue we try to fix for the P-tile simulation tools.
To work around this problem, use Siemens* Questa Sim-64 2022.2. Starting in the Intel® Quartus® Prime Software version 23.3, solve this issue by adding this command " set USER_DEFINED_ELAB_OPTIONS "-voptargs=\"-noprotectopt\" before running simulation in the Siemens* Questa Sim.
Detail you may refer to https://www.intel.com/content/www/us/en/support/programmable/articles/000092901.html
Hope that is able to help you to move forward,
Regards,
Wincent_Intel
Regular ContributorHi,
No specific signals are being monitored . The goal is to run the simulation faster to integrate and verify our user logic along with the BFM.
>> temporary the simulation time up to hours is expected. Due to large IP configuration.
>> I do apology if there is any inconvenience causing to you if have.
>> The best thing I could help is to address this to our design team, hope they can find a way to optimize this better in future release of software.
2.We suspect that the p0_reset_status_n signal is delayed in our environment, as it is asserted only after 100,000 ns. Could you please check in your environment when this signal is asserted for both the Root Port (RP) and Endpoint (EP) and when was the link training initiated ?
>> May I know which device OPN that you are using ?
>> try to run the same so that we have apple to apple comparison.
Regards,
Wincent
New ContributorHi wincent,
Could you clarify the exact simulation time in hours when running in VCS ?
The device we are using is a Stratix 10, specifically 1SD110PJ2F43E2VG. We have also tested on other boards supporting P-Tile, and the results show similar simulation times in quest sim . Could you share your experimental results for comparison in questa sim?
Regards,
Thana Vignesh
- Wincent_Altera
Hi Thana,
Please allow me to have sometime to try out the simulation, update you the time once I have it finish.
Again, I would like to emphasize that simulation time up to hours is expected. Due to large IP configuration.
Regards
Wincent - Wincent_Altera
Hi Thana,
Sorry for late, I was occupied with some other important agenda.
I am able to run and capture the signal via Questa Sim 2023.4 version based on your device#
I forget to record the time while leaving it run overtime, it shall be less than 6-8 hours
Regards,
Wincent - thanavignesh
Hi Winicent,
After configuring the P-Tile as a Native Endpoint IP and providing all the necessary settings in the GUI, if we program it onto the Stratix 10 board, will the enumeration take place? How can we verify if the enumeration was successful? We are using a Stratix 10 board with Quartus version 20.3. Which signals, such as ninit_done, ref_clk[1:0], and reset, need to be connected for the P-Tile IP? Is there a user guide that explicitly outlines these requirements?
RegardsThanavignesh
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