Forum Discussion
New ContributorIssue with Simulation Stalling in Intel P-Tile Streaming PCIe Gen4 x8 Example Design
Hi,
I am Wincent, Application Engineer from Altera.
We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries.
Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended.
May I know which Questasim version that you are using?
There is an known issue we try to fix for the P-tile simulation tools.
To work around this problem, use Siemens* Questa Sim-64 2022.2. Starting in the Intel® Quartus® Prime Software version 23.3, solve this issue by adding this command " set USER_DEFINED_ELAB_OPTIONS "-voptargs=\"-noprotectopt\" before running simulation in the Siemens* Questa Sim.
Detail you may refer to https://www.intel.com/content/www/us/en/support/programmable/articles/000092901.html
Hope that is able to help you to move forward,
Regards,
Wincent_Intel
New ContributorHi Wincent,
With the default settings and only the change to Gen 4x8 configuration, it takes around 8 hours to complete without any signals logged.
To debug this further, could we arrange a call to discuss the issue in detail? I can share the .ip file and any other necessary files during the call for better clarity. Please let me know a convenient time, and I’ll make the arrangements.
Regards,
Thanavignesh
New ContributorHi Wincent,
Are there any specific system requirements, such as having 100GB of RAM, to achieve faster simulation performance for the P-Tile example design in Questa Sim?
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