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fa_fpga_enthusiast's avatar
fa_fpga_enthusiast
Icon for Occasional Contributor rankOccasional Contributor
9 months ago

Issue with BSP Creation for Nios-V/m Using LPDDR4 on Agilex-5 (Quartus 24.1 & 24.3.1)

Hello, We are encountering an issue while creating a BSP for the Nios-V/m targeting Agilex-5 using LPDDR4 as the processor memory. We have attempted this using Quartus 24.1 and 24.3.1 but faced the ...
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tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
7 months ago

Hi


Thanks for sharing the connection.

Yes the s0_axi4_ctrl_ready needs to be connected to the nios reset input.

The logic behind this connection is s0_axi4_ctrl_ready is an output reset signal to keep the Nios in reset until the DDR calibration is completed.


You could find the documentation on the signal below:https://www.intel.com/content/www/us/en/docs/programmable/817467/25-1/s0-axi4-ctrl-ready-for-agilex-5-e-series-62430.html


Regards

Jingyang, Teh