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fa_fpga_enthusiast
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9 months ago

Issue with BSP Creation for Nios-V/m Using LPDDR4 on Agilex-5 (Quartus 24.1 & 24.3.1)

Hello, We are encountering an issue while creating a BSP for the Nios-V/m targeting Agilex-5 using LPDDR4 as the processor memory. We have attempted this using Quartus 24.1 and 24.3.1 but faced the ...
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fa_fpga_enthusiast's avatar
fa_fpga_enthusiast
Icon for Occasional Contributor rankOccasional Contributor
8 months ago

Hello,

After connecting the s0_axi4_ctrl_ready signal of the EMIF IP core to the reset ports of both the Address Span Extender and the Nios® V processor, the issue no longer occurs.

We can now successfully use the LPDDR4 as the program memory for the Nios® V processor.

Please note that we were unable to find any information regarding the s0_axi4_ctrl_ready signal in the External Memory Interfaces (EMIF) IP User Guide.

Thank you for your support.

Best regards,