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fa_fpga_enthusiast
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9 months ago

Issue with BSP Creation for Nios-V/m Using LPDDR4 on Agilex-5 (Quartus 24.1 & 24.3.1)

Hello, We are encountering an issue while creating a BSP for the Nios-V/m targeting Agilex-5 using LPDDR4 as the processor memory. We have attempted this using Quartus 24.1 and 24.3.1 but faced the ...
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fa_fpga_enthusiast's avatar
fa_fpga_enthusiast
Icon for Occasional Contributor rankOccasional Contributor
8 months ago

Hello,

Thank you for your response.

You might not be seeing the warning because the "altera_address_span_extender_hw.tcl" file was not modified as we previously explained. Without this modification (or a similar one), how can the Address Span Extender be recognized as visible memory for the processor when generating the BSP?

Even if we attempt to define the memory regions manually, we are unable to select the Address Span Extender when pressing the "Add" button—unless the mentioned TCL file is already modified.

Additionally, manually defining memory regions every time we generate the BSP is not an ideal solution. We expect the tool to handle this automatically.

Also, we tried "Assign Base Address", "Assign Interrupt Number," and "Sync System Infos", but the warning is still there.

A screenshot is attached showing where the warning appears.

We are using Quartus 24.3.1.

Looking forward to your thoughts.

Best regards.