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fa_fpga_enthusiast's avatar
fa_fpga_enthusiast
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Issue with BSP Creation for Nios-V/m Using LPDDR4 on Agilex-5 (Quartus 24.1 & 24.3.1)

Hello, We are encountering an issue while creating a BSP for the Nios-V/m targeting Agilex-5 using LPDDR4 as the processor memory. We have attempted this using Quartus 24.1 and 24.3.1 but faced the ...
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tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi


Apologies for the late response.

In my project I tried adding the Address span extender and did not see the warning mention when generating the BSP.

Could you try "Assign Base Address", "Assign Interrupt Number" and "Sync System Infos" to see if this warning is still there?

After the BSP generation, it will not auto detect the memory region. You would need to manually define the memory region.


Regards

Jingyang, Teh