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Altera_Forum
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8 years ago

issue with avalon streaming witdth convertion

hi, everyone! I am new to FPGA and NIOS I was trying to capture frame from the vip test pattern generator and write to sdram using SGDMA. But the data came from the test pattern generator was 24...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

That RTL looks fine to me, I would check the logic that is driving data_in to make sure the issue isn't occuring before data arrives to your block. Look for warning messages in the compilation console at the bottom of Quartus for things like unconnected nets, stuck bits, etc...