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Altera_Forum
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8 years ago

Issue with 245 Fifo sync mode

Dear All, I am actually working on a communication chain between a FPGA and a FT2232H chip. So, the goal is to send a file from PC to FPGA, store it in a FIFO memory and then receive the se...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

I believe what I saw (years ago) was a situation in which RXF (or TXF) was in a high state, then it momentarily glitched low when it should have remained high. This created problems with the state machine in the FPGA.