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Honored Contributor
Honored ContributorIssue with 245 Fifo sync mode
Dear All, I am actually working on a communication chain between a FPGA and a FT2232H chip. So, the goal is to send a file from PC to FPGA, store it in a FIFO memory and then receive the se...
Altera_ForumHonored Contributor
Honored ContributorIt could still be a timing problem. Do you need to set any input/output delays on your IOs to compensate for trace delays?
