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Matt1's avatar
Matt1
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5 years ago

issue in routing HPS I2C to FPGA in A10 SoC

Hi, I have a requirement to route the I2C(master) in HPS to FPGA and connect the I2C signals to an I2C slave IP(IO Expander logic).I tried to in the following way under parameter(hard processing...
Eliath_G_Intel's avatar
Eliath_G_Intel
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hello Nithin,


Yes, SCL is provided by the master.


SCL is not only the clock, it is also used to receive the acknowledge signal from the slave.


Regards,

-Eliath Guzman


Matt1's avatar
Matt1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

hello Eilath,

yes the clock should be supplied from the master,

here is my point ,when we route the I2C from HPS to FPGA we have the following signals available

since SCL signal is specified as input , then it can only receive the clock, it cannot drive any clock!!

So what I understand from the port list is that, the IP is a slave.

I am looking for the Master I2C from HPS ,accessible to FPGA to connect to a slave in FPGA.

*I think, SDA signal receive the acknowledge signal from the slave, not the scl.