is there any option to change the data width of Avalon interface in ddr3 controller?

Dear sbala31,

Thank you for joining this Intel Community.

I assume right now your DDR3 DQ = 16 bits (Quarter rate) and this will provide Avalon (amm) data wide of 128 bits. Also, are you using hard interface?

If above assumption is correct, then to have the amm data width requirement, you have to tick “enable error detection and correction logic with ECC” in your EMIF GUI (see screenshot below). After this tick, it will convert the amm data width from 128 to 64 bits (refer to block diagram highlighted in yellow).

For 16 bits interface, usually the extra 8 bits is user for error detection and we only use 8 bits for data. For more details about the Error Correction Code (ECC), you may refer to this EMIF Handbook Vol.3 in below link, search for ECC :

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_ip.pdf

Another option is you can reduce the DDR3 DQ width to 8 bits without enabling the ECC. So, either make the interface 8 bits wide or keep it as 16 bits wide and enable ECC to get the amm data width requirement (64 bits).

I sincerely hope this helps. 😊

Thanks

Regards

Aida