Is there a way for CvP over PCIe to do CvP update?

​Hi, it is understood that both V and 10 series require logic partition between periphery and core. But the V series document ug_cvp.pdf never mentions a requirement to physically partition and lock the core region. The main disadvantage of the Stratix 10's CvP is that it requires physically partition and lock the core region (aka, place and route). Unless the V series ug_cvp.pdf document is incorrect, the CvP Updates between V series and 10 series are different. V series CvP Update is similar to CvP Initialization while 10 series CvP Update is actually a subset of PR. Looks like even though V series document clearly states that CvP Update feature will be gone, another Intel team developing 10 series mistakenly used the term CvP Update for what is actually a PR with automatic (transparent) insertion of PR controllers and with limitation of what the "persona" should be.