Is there a way for CvP over PCIe to do CvP update?

​Hi,

By reading thru the ug-s10-cvp.pdf, it appears that the Stratix 10's so-called CvP Update is very similar to Arria 10's Partial Reconfiugation in the way that it requres physically partitioning and locking a region, in this case, the so-called "core region". The only difference is that it appears that it does not require manually instantiating PR controller and PR region controller. The true CvP Update mode that existed in eariler devices that does not require physically partioning and locking any region no longer exist in Stratix 10. Can Intel clarify what is going with Stratix 10's CvP Update? If the ug-s10-cvp.pdf is correct, the Stratix 10's CvP Update mode is not as robust or flexible as Arria 10's Partial Reconfuration that allows precise control of start and stop of PR and as well as multi-region PR. In Intel's product road map, except device size, is Arria 10 more advanced in Intel's device development (it looks like Arria 10's PR is more advanced that Stratix 10's CvP Update that is a shrunk version of PR)? Does Stratix 10 support Partial Reconfiguraton (essentially the question may be equivalent to "Does Stratix 10 have PR controller and PR region controller)? Thanks.