Is there a 10GBASE-R with 1588 reference design for Stratix 10 L/H Tile Transceiver?

Hi,

Sorry for the late respond as I was waiting for Intel internal team to publish another 1588 reference design to better answer your questions here.

For below S10 1588 design example

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20073.pdf
• It just provide timestamp and doesn't provide additional PTP time adjustment which correlate with your understanding and questions

For below latest S10 1588 reference design (that just got published last week)

• https://rocketboards.org/foswiki/Projects/Stratix10SoCDesignExampleFor10GbeWithIEEE1588PTPCapability
• This reference design contains the PTP clock adjustment algorithm driver but this is software design that run with CPU in Linux, not RTL state machine design feature that build inside Intel FPGA Ethernet IP that you are looking for

Thanks.

Regards,

dlim