Altera_Forum
Honored Contributor
Honored ContributorIP core optimization
Hi everyone, How can I optimize any IP core for Altera FPGA technology? What kind of care needs to be taken when optimizing for particular FPGA technology or ASIC?
Forum Discussion
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- ... I wanted to know if there is any thumb rule! --- Quote End --- The optimization advisors in Quartus that I mentioned cover most of the things that I usually try first like optimization technique in Analysis & Synthesis and physical synthesis for performance in the Fitter. The advisors also suggest things that I rarely bother with such as optimizing state machine encodings (probably not worth the trouble unless you have a huge state machine or your worst timing violations are in a state machine) and LogicLock (helps speed in only a few designs, and can make things worse if done wrong). Start with the advisor recommendations that are the easiest to try. Many are simple setting changes that can be done right in the advisor window.
