Honored Contributor
Honored ContributorHi Kaz,
about the block, I was meaning the VHDL component generated by the IP Compiler, which looks like this: component FIR_stage_1 is port( clk : in std_logic := '0'; -- clk.clk reset_n : in std_logic := '0'; -- rst.reset_n ast_sink_data : in std_logic_vector(71 downto 0) := (others => '0'); -- avalon_streaming_sink.data ast_sink_valid : in std_logic := '0'; -- .valid ast_sink_error : in std_logic_vector(1 downto 0) := (others => '0'); -- .error ast_source_data : out std_logic_vector(203 downto 0); -- avalon_streaming_source.data ast_source_valid : out std_logic; -- .valid ast_source_error : out std_logic_vector(1 downto 0) -- .error ); end component; Inside the FIR II Compiler I have defined an input bit width of 12 bits, but the avalon_sink_data input is 72 bits wide, for this I don´t understand how I should use the megacore to filter my signal. Unluckily I don´t have a license for the DSPBuilder, so I need to work just inside quartus and write down the code myself. About the signal´s speed, I was reading that the MLABs inside the Stratix IV 530 GX can work up to a maximum of 600 MHz, in past I have already experienced some issues while trying to realize a dual tone generatore on my chip.I would like to use FIR filters in order to realize a digital down converter.
