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Hello to everyone,
I would like to make a quesiton about the way the FIR II IP compiler should be used. I have read the documentation, and I have easily instantiated the FIR filter by using the FIR II Compiler from the plugin wizard.
What I would like to do, is just to obtain a simple low pass filter, working on a digital signal with 12 bit samples at a speed of 600 MSPS. What is still not clear to me is, why when I set the input signal dimension to 12 bits, I get from the gui of the megacore that the output is about 34 bits? Is the first time that I am approaching to this IP and I am a little bit lost.
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I haven't used FIR compiler but pretty familiar with DSPBuilder filters. Your speed of 600Msps can't be done in any FPGA I know. Hopefully a typo.
Output bitgrowth follows sum f products of all coefficients and so grows accordingly(if your data is 12 bits and coeffs 12 bits then every product will have bitwidth of 24 bits and sum of two products will need 25bits and so on.)
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I see that input and outputs of the block, are respectively 72 and 204 bits wide.....could someone give me a tip on how can I include this block into my design? For now I would be already grateful if I could run an easy FIR filter with the wanted behavior. Is there online any example or tutorial on how to use this block correctly?
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which block?
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