interrupt for pci ip core

Hi,

i create a pci t32 project with sopc builder,

the bars i used are:

0: prefetachable for on-chip ram access

1: non-prefetachable for csr access.

now i can read/write on-chip ram.

and when i write to csr's 0x40 from pci host, it works ok too.

but when i read csr's 0x50/0x40 from pci host for interrupt information, it hange.

The host system is amd lx800, w/ quartus 8.0 could anyone help me?