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jg_UF's avatar
jg_UF
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4 years ago

Interfacing with HBM2 on Stratix 10 MX using Reference Design

Hi, This is a follow up to the thread at https://community.intel.com/t5/FPGA-Intellectual-Property/HBM2-interfacing-with-the-PCI-express-hard-IP-STRATIX-10-MX/td-p/1233329/page/2. We are tr...
Deshi_Intel's avatar
Deshi_Intel
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4 years ago

Hi Justin,


Just to confirm again are you using Quartus v19.2 specifically as the reference design is validated with v19.2 only ?


And also to confirm the failure only occur after you made modification to the reference design, right ?

  • The failure occurs on the path where your kernel application is transferring data to HBM2 ? May I know is this using PCIe as well or via other protocol ?


You mentioned the failure only occurs once you transfer data exceeding certain limit. Maybe you can

  • Check on your back pressure design block if it's present in your design implementation
  • Check your software application driver - buffer design to ensure it can cater for big data transfer
  • Ensure your FPGA quartus design is timing clean
  • If you really want to drill down further into debugging then you need to start to signal_tap the AXI master -> whatever interconnect block -> HBM2 soft interface to slowly isolate where is the failure point


Thanks.


Regards,

dlim


  • jg_UF's avatar
    jg_UF
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    4 years ago

    Hi dlim,

    I made a mistake in my last message. We are not modifying the reference design, just using the 'AXI Bridge' component that merges the two HBM2 pseudo-channel AXI4 interfaces. The failure only occurs when we use this component in our own design (i.e. when we wish to have a 512-bit wide AXI4 interface between kernel and 2 HBM2 pseudo-channels). We do not run into any error when this component is omitted (when we instead use a 256-bit wide AXI4 interface between kernel and 1 HBM2 pseudo-channel).

    We've been using Quartus v19.4, and are limited to this version because of the PCIe FPGA Board that we are using. Is there anyway around the fact that the reference design is only validated for v19.2? Is there by chance another IP that just merges two AXI4 interfaces, that has been validated on v19.4?

    Thanks for the debugging pointers; I will begin looking into these.

    Justin