Interfacing with HBM2 on Stratix 10 MX using Reference Design

Hi dlim,

Unfortunately the error is still encountered when using the latest reference design. I will provide some details on the error and our design below:

We are attempting to modify the reference design to provide HBM2 access to an application kernel on the FPGA fabric. This is currently being done by MUXing two AXI4 master interfaces, one from the AVMM PCIe IP and the other from the application kernel, for connection to the AXI bridge that merges the HBM2 pseudo-channels.

We use our own created AXI4 master interface component to facilitate transfers from the application kernel to HBM2. This component uses FSMs for each AXI4 channel (aw, w, b, ar, r) and FIFOs, to allow for data to be pipelined in/out of the application kernel to/from HBM2. The error takes the form of a hang, and occurs specifically when we attempt to transfer more than 256 data words “in a row” (our AXI4 component accepts a ‘size’ signal which determines how many reads/writes to send in a row, controlled by the FSMs).

We do not think that our AXI4 master interface component is the failure source: when interfacing with just one of the HBM2 pseudo-channels (using only 256-bit bandwidth and as such not using the AXI bridge component from the reference design), no errors are encountered. I’ve been looking primarily into the axi_bridge_to_hbmc_if.v file from the reference design, as it seems to contain all the AXI4 interface merging logic, but have yet been unable to find a bug that would cause the error we’re seeing.

I’d greatly appreciate any ideas you have on what could be causing this, or any debugging advice.

Thanks,

Justin