Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Interfacing Avalon On-Chip Memory Core to a custom Avalon MM Master

Hello, I am trying to implement a custom Avalon MM Master to write into an On-Chip memory. This memory will later be accessed by a PCIe megafunction. My input is a data stream from a camera. As...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

You could have the waitrequest signal, and assign it to zero within your module. This way "Error: memory.onchip_memory2_0.s1: Master avalon_master_1_1_1_1 does not have a waitrequest signal. Slave must match master's read and write wait time (read:1 write:1)" will not be an issue and your functionality will not change.